1. Technical Field of the Invention
The present invention generally relates to an interface between a single channelized input and multiple outputs. More particularly, and not by way of any limitation, the present invention is directed to system and method for implementing flow control with dynamic load balancing in such interfaces.
2. Description of Related Art
Currently, there exists an interface device for translating System Packet Interface level 4.2 (“SPI4.2”) to Generic Media Independent Interface (“GMII”). A single channelized input, such as is the case with SPI4.2, means one input port (e.g., a SPI4.2 port) with many channels, where each channel might carry traffic of a particular priority. FIG. 1 illustrates interface logic (“IL”) circuitry 100 for translating between a single channelized SPI4.2 input port 102 at 2.5 gigabits-per-second (“Gbps”) and three GMII output ports 104a-104c at 1 Gbps each.
As illustrated in FIG. 1, an SPI4.2-to-GMII interface, such as the circuitry 100, requires flow control due to a rate mismatch between the 2.5 Gbps input and the 1 Gbps output. Without flow control, packets enter the IL circuitry 100 at a higher rate than can be siphoned out. Accordingly, packets or parts of packets are dropped without indication thereof being sent to the SPI4.2 input port 102. As a result, the GMII output ports 104a-104c may receive only a portion of a packet coming in from the input port 102. Corrupt data sent upstream could cause waste of resources, delays, and shutdown of the IL circuitry 100.
Additionally, an SPI4.2-to-GMII interface, such as the circuitry 100, requires load balancing amongst the GMII ports 104a-104c to ensure that traffic is equally distributed therebetween. Dynamic load balancing is required in the event that traffic to one of the GMII ports 104a-104c becomes excessive. Without dynamic load balancing, new incoming traffic flows would continue to be assigned to heavily loaded ports, resulting in inefficient use of resources and bandwidth waste.
Currently, there is no known mechanism for performing flow control with dynamic load balancing in protocol translation interfaces. One chipset, referred to herein as “Vitesse7321”, maps SPI4.2 to GMII; however, each SPI4.2 channel is mapped to a single GMII port. Moreover, the Vitesse7321 does not implement true flow control. Rather, excess traffic coming in on the SPI4.2 channel, at rates beyond 1 Gbps, is dropped without sending any backpressure mechanism to the SPI4.2 interface. Additionally, designs that implement SPI4.2 to SPI3 bridges translate Quad SPI3 to SPI4.2; however, these do not require flow control because no rate mismatch is encountered. Also, it is known that problems such as these are commonly encountered in implementing other protocol translation interfaces in general.